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Altera_Forum
Honored Contributor
13 years agoYou need to find yourself a good VHDL book.
Your code does not need the keywords 'PROCESS', 'BEGIN', 'END PROCESS', since you have not created any code that needs to go in the process. For type conversion, you need to look at what the numeric_std library provides. Hint: to_integer, but it takes an unsigned, so you need to figure out how a std_logic_vector gets converted to unsigned, and then convert unsigned to integer. Your code will look like s <= to_integer(<something here>(rand_temp)); I don't want to spoil your chance to learn by giving you all the details, so please search around and try to figure it out. Cheers, Dave