Gate-level Simulation

Question

Hi ,

I am working on a design , it has a top level VHDL file ( a main state machine in it) and then a UART is enabled from this Main ( State machine ) .

Everything works fine in RTL simulation . But when i switch to Gate-level Simulation i dont see any response or even glitch when UART is enabled .

This is using Quartus-II ver 10.0 and Altera-Modelsim .

When i compiled the design in Xilinx , again it failed in Gate-level but before shutting down it spite out a message about Modelsim couldnt handle 10K lines of code .

Any clues ???

Thanks in advance.

altera_forum · Answer

In Gate Level, UART signal are stable or do they have a x or z value? In Gate level the FSM signal are properly switching?

altera_forum · Answer

In Gate Level it wont start , not even show any glitch . Just stay dorment . I have traced the enable signal , it is valid but the UART State machine wont kick start .

altera_forum · Answer

What is that doesn't start? Modelsim? The Uart? The FSM?  If Modelsim starts, do you see the input signal that switch? Do you see the outputs of the FSM that switch?

altera_forum · Answer

What is that doesn't start? Modelsim? The Uart? The FSM?     ans: The UART    Have a look at the screen shot of RTL and Gate Simulation.

altera_forum · Answer

the "gate" is the transmit start signal  and "serial_out" is the serial data out signal .

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Gate-level Simulation

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