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Altera_Forum
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16 years ago

Gate-level Simulation

Hi , I am working on a design , it has a top level VHDL file ( a main state machine in it) and then a UART is enabled from this Main ( State machine ) . Everything works fine in RTL simulat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

What is that doesn't start?

Modelsim?

The Uart?

The FSM?

If Modelsim starts, do you see the input signal that switch?

Do you see the outputs of the FSM that switch?