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Altera_Forum
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15 years ago

Gate-level Simulation

Hi , I am working on a design , it has a top level VHDL file ( a main state machine in it) and then a UART is enabled from this Main ( State machine ) . Everything works fine in RTL simulat...
Altera_Forum's avatar
Altera_Forum
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15 years ago

the "gate" is the transmit start signal

and "serial_out" is the serial data out signal .