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Altera_Forum
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16 years ago

Gate-level Simulation

Hi , I am working on a design , it has a top level VHDL file ( a main state machine in it) and then a UART is enabled from this Main ( State machine ) . Everything works fine in RTL simulat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The RTL simulation screenshots you've posted don't cover the same time frame as the gate-level simuation screenshots.

Also, I'd also suggest that you take a good look at the uut input and output signals, in order not to hide any missing connections

For example, I don't a /tb_ssi/uut/clk signal in the simulations. I guess it's problably the same signal as one of the /tb_ssi/clk* signals, but I don't know which.

This makes it impossible to compare your results.