FPGA schematic design - JTAG and EPCQA

Hello,

I am designing a custom board with Cyclone 10 LP FPGA - 10CL080YU484A7G. I have the following questions:

a) Should the VREFB pins be connected to Ground or VCCIO? I use same IO voltage of 1.2V for all banks.

b) Cyclone 10 Handbook mentions that pull up resistors of FPGA device to be connected to VCC of the bank in which the JTAG pins reside. I do not understand this point. Could you please elaborate? Is this a setting in Quartus Prime? Or any connections to be made in the board schematics?

Is this anything related to RUP and RDN pins of FPGA? I am using some of the RUP and RDN as user IO.

I am using the SFL core for in system configuration using JTAG. Supply voltage to JTAG connector is VCCA (2.5 V in my case). If JTAG signals are at VCCA (2.5V logic) and VCCIO of FPGA is 3.3V, will this work?

Thank you!