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NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

FPGA schematic design - JTAG and EPCQA

Hello, I am designing a custom board with Cyclone 10 LP FPGA - 10CL080YU484A7G. I have the following questions: a) Should the VREFB pins be connected to Ground or VCCIO? I use same IO voltage of...
AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hello,

Please refer to these links for your reference design:

1. Cyclone 10 LP GPIO User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.pdf

2. Cyclone 10 LP Device Datasheet: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51002.pdf

3. Cyclone 10 LP Pin Connection Guideline: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01021.pdf

The answer is yes to the second question. You can use Pin Planner to program this setting.

Please refer to I/O Standard table from page 78 and see your setting meet the guideline.

Thank you.