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NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

FPGA schematic design - JTAG and EPCQA

Hello, I am designing a custom board with Cyclone 10 LP FPGA - 10CL080YU484A7G. I have the following questions: a) Should the VREFB pins be connected to Ground or VCCIO? I use same IO voltage of...
NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hello,

Thank you for your answer. I have referred the documents.

It is still not clear for me: "pull up resistors of FPGA device to be connected to VCC of the bank in which the JTAG pins reside"

The above diagram shows the JTAG connector pins are connected to VCCA, which is 2.5 V and FPGA pull ups connected to VCC of the bank i.e VCCIO = 3.3V. Is this not a mismatch?

AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hello,

That is the guideline where you configure Intel Cyclone 10 LP Device where you need to connect the pull up resistor of the device to Vcc in which the pin resides.

You can configure pins using Pin Planner.