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Altera_Forum
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16 years ago

FPGA Powering PCB Guidelines??

Could someone provide some PCB design guidelines concerning powering my EP3C16Q240 FPGA? I can only use a 2 layer design, and I need 1.2 V to power the FPGA core and 2.5 V to power all the I/O buffers. Should I use some kind of "voltage bus" for each of the voltage values then connect each pin to those buses and decouple accordingly with capacitors? What if just I connect the voltage pins (of the same value) together, then connect some of them to the corresponding voltage regulator? Would this cause some of those pins to receive reduced voltage and even design failure?

Thanks

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    This has been discussed several times and some users have succcessfully done that.

    what is you fmax ?? internal & external

    but i would strongly recommend to go for at least a 4 layer pcb if you have any chance to do so.

    if not, make those power traces wide (to lower their resistance and inductance)

    make those traces as short as possible

    whenever possible try to make a star connection from volatge source to the pins or sums of pins instead of one track going round and round

    you can connect pins together when they are connected to the same voltage.

    if possible place more than one via on those power traces to lower down the inductance you get with a via.

    as you do not have enough planes for impedance a controlled power supply take care about the caps you are using. have a look at the ESR

    when setting up quartus, check the pins settings for current limiting to prevent over and under shots)

    if you encounter problems with the design, have a look at ground bouncing, voltage undershots can move the trigger levels so your logic might think thare is a edge when there is none.

    obey the pll power supply recomendations for this device family if you intend to use a pll

    last but not least, your power supply should be capable to handle those fast transients due to switching of you fpga.

    good luck !

    (and have fun :-) )
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You have to power the PLL pins (both digital and analog) whether you use the PLL's or not. That means that for most systems with 3.3V logic, you have three voltage rails. I suspect you *could* pull off a two-layer board, but you might end up with a "third" layer of wire jumpers. You do have to watch for inductance problems if you aren't using planes, so be sure that if you are using PLL's, you keep the traces or jumpers to the power supply short, and decouple them adequately. The bigger problem with a two-layer board is the lack of a proper ground plane. If you can manage to arrange your board so you can keep a large area under the FPGA clear for a "mini" ground plane and decoupling caps, that would help a lot. You can still leave the area under the pads free for vias, especially on a large QFP, like the 240, and stuff a fairly decent number of coupling caps in the center. I've even got a card that places the 1.2 and 2.5V regulators under the FPGA - but that's a four layer card with a ground plane. I will say, switching to a four-layer board will dramatically simplify your life, and make the odds of success much higher. At four layers, you can have an entire layer for ground (a huge bonus) and carve out voltage planes for the FPGA and other IC's. I've done several Cyclone 3 designs on 4-layer boards, and I've just about got the power plane design down pat. I'm not saying it can't be done, but I can't see how your power distribution will be anything better than marginal on a two-layer board.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    just an additional note here :

    --- Quote Start ---

    a large area under the FPGA clear for a "mini" ground plane

    --- Quote End ---

    such a smal copper area can't be called plane. it is just a solid fill

    If you assume the thickness between the two copper sides then there won't be a low Z.

    Just calculate the Z for 50um and 100um distance to see the effect and now imagine a pcb with normaly 1500um ...

    also with an eye on impedance, the area underneath a qfp is too smal that it will have an effect on the lower frequencies for decoupling. here the caps will do the work.

    but again even the position of these caps and their value needs to be carefully calculated that you won't get a high Z for certain frequencies. at those frequencies the pcb will radiate like a good antennae

    there are some (not free) tools out there, that display the impedance Z of the pcb over the pcb area as a 3D diagramm and you can see how Z changes due to the position of the caps (and the values)

    and if that is not enough ... the shape of these planes have a not to neglect effect

    okay ... i am in a lucky postion to have such a tool and it helped me to pass all approvals with the first pcb design without any housing or shielding at all.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thank you for your replies. I m still forced to have a 2 layer design though, so I have to make this work :) I am thinking of trying something like this. Of course this is a pre copper pour design.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    well, you could try it.

    but always take into account that trace have inductance and that is not what we need.

    so make traces as soon as possible wide. imagine some kind of teardrops ...
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    yes, make those supply traces as WIDE ;) as you can.

    but don't forget the return current on GND for powersupply nets and IOs as well
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    but don't forget the return current on GND for powersupply nets and IOs as well

    --- Quote End ---

    What do u mean by that? Can u be more specific please?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    the current that flows into a pin must return somewhere, hopefully a GND pin

    the current in combination with the resistant of a track leads to a voltage drop across this track.

    so you have static currents and dynamic currents due to switching of logic

    your current is the combination of both

    now think a bit complex about lots of current peaks of different amplitudes and frequencies

    so your voltage drop is now always the same and when your traces are to smal, you add inductance (what you should avoid)

    so the currents comes from your power supply systems and the must return there to close this loop. energie is never lost it is only transformed. in best case into heat and not radiated (EMC)

    keep the currentflow between power supply and device and back as close as possible

    imagine a loop antennae with 1 winding and your task is to minimize this area inside this loop.