FPGA Powering PCB Guidelines??

This has been discussed several times and some users have succcessfully done that.

what is you fmax ?? internal & external

but i would strongly recommend to go for at least a 4 layer pcb if you have any chance to do so.

if not, make those power traces wide (to lower their resistance and inductance)

make those traces as short as possible

whenever possible try to make a star connection from volatge source to the pins or sums of pins instead of one track going round and round

you can connect pins together when they are connected to the same voltage.

if possible place more than one via on those power traces to lower down the inductance you get with a via.

as you do not have enough planes for impedance a controlled power supply take care about the caps you are using. have a look at the ESR

when setting up quartus, check the pins settings for current limiting to prevent over and under shots)

if you encounter problems with the design, have a look at ground bouncing, voltage undershots can move the trigger levels so your logic might think thare is a edge when there is none.

obey the pll power supply recomendations for this device family if you intend to use a pll

last but not least, your power supply should be capable to handle those fast transients due to switching of you fpga.

good luck !

(and have fun :-) )