FPGA Powering PCB Guidelines??

the current that flows into a pin must return somewhere, hopefully a GND pin

the current in combination with the resistant of a track leads to a voltage drop across this track.

so you have static currents and dynamic currents due to switching of logic

your current is the combination of both

now think a bit complex about lots of current peaks of different amplitudes and frequencies

so your voltage drop is now always the same and when your traces are to smal, you add inductance (what you should avoid)

so the currents comes from your power supply systems and the must return there to close this loop. energie is never lost it is only transformed. in best case into heat and not radiated (EMC)

keep the currentflow between power supply and device and back as close as possible

imagine a loop antennae with 1 winding and your task is to minimize this area inside this loop.