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Altera_Forum's avatar
Altera_Forum
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13 years ago

FPGA pin assignments - is it good to breakup the buses

Hi,

I've got an FPGA sending out two buses (16-bit buses) to a DSP. I'm also sending with the two channels a clock and a frame sync. What is the general rule of thumb when assigning FPGA pinouts for them?

I usually keep the buses on the same IO bank. However, the layout guy has split the two channels among two adjacent IO banks. I'm wondering if this is ok as long as both channels, the clock, and frame sync are length matched for the traces and I meet timing for the FPGA. Or is this a case of the layout guy trying to make his life easier and my life a little harder.

Also, should I be concerned about crosstalk among the buses and too many simultaneously switching traces if both 16-bit buses are kept on the same IO bank. The clock rate I'm at is 30 MHz and LVCMOS 3.3 (possibly switching to LVTTL 3.3V)?

Thanks,

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    At 30 MHz I wouldn't worry too much. So long as you setup your timing constraints, you shouldn't have much of a problem. Stick with the voltage requirements of your DSP (LVCMOS vs LVTTL)

    The only thing I would worry about is if you have different voltage requirements on the same bank. (some pins at 3.3 and some at 2.5 etc)
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi kosh271,

    Thanks for the input.

    Initially, the constraints are set for 3.3V LVCMOS, but since I can't get the higher current drive strengths for the Arria II device at LVCMOS I'm changing the IOs to be at 3.3V LVTTL. The IO banks are still powered off of 3.3V.

    By the way, was there a rule some place about how every 1 cm of trace length = 7 ns of delay for a signal or something like that? Not sure where I heard this rule of thumb.

    Thanks,