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Altera_Forum
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13 years ago

FPGA pin assignments - is it good to breakup the buses

Hi, I've got an FPGA sending out two buses (16-bit buses) to a DSP. I'm also sending with the two channels a clock and a frame sync. What is the general rule of thumb when assigning FPGA pin...
Altera_Forum's avatar
Altera_Forum
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13 years ago

At 30 MHz I wouldn't worry too much. So long as you setup your timing constraints, you shouldn't have much of a problem. Stick with the voltage requirements of your DSP (LVCMOS vs LVTTL)

The only thing I would worry about is if you have different voltage requirements on the same bank. (some pins at 3.3 and some at 2.5 etc)