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Altera_Forum
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13 years ago

FPGA pin assignments - is it good to breakup the buses

Hi, I've got an FPGA sending out two buses (16-bit buses) to a DSP. I'm also sending with the two channels a clock and a frame sync. What is the general rule of thumb when assigning FPGA pin...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Hi kosh271,

Thanks for the input.

Initially, the constraints are set for 3.3V LVCMOS, but since I can't get the higher current drive strengths for the Arria II device at LVCMOS I'm changing the IOs to be at 3.3V LVTTL. The IO banks are still powered off of 3.3V.

By the way, was there a rule some place about how every 1 cm of trace length = 7 ns of delay for a signal or something like that? Not sure where I heard this rule of thumb.

Thanks,