FPGA packages for PCB design

There are footprints for Cadence tools here: http://www.altera.com/download/board-layout-test/pcb/pcb-cadence.html and for Mentor Graphics tools here: https://www.altera.com/download/board-layout-test/pcb/pcb-mentor-graphics.jsp

I'm not sure that any of them would work with EAGLE.

Thanks for the links! Unfortunately I didn't manage to use them in EAGLE. I managed however to write a small script which uses a CSV file exported from the Excel files downloadable from http://www.altera.com/literature/lit-dp.jsp?category=cyc%203&showspreadsheet=y to create the EAGLE schematic symbol and link it to a predefined EAGLE package...

I'll attach the script here as soon as it's ready :)

I looked extensively for a suitable library part when I began my design for a 1517 pin package. The only thing available is are scripts that make a simple X,Y grid of identical pins. For such a customizable chip, I considered this completely inadequate.

I went several steps further. Altera has Excel spreadsheets for the different FPGAs. I used one of them as a basis for generating my script. In Excel, I split the pin numbers into the lettered part (A,B,C,... AK, AL, etc) and the numbered part (1-39). Formulas found the X and Y offset of the pin using VLOOKUP into a table of values. Pad sizes, solder mask sizes and such were entered as variables. By the final column I had a text line composed that would generate all the components of the pin on a variety of different layers. I also made overlay layers for marking special pins, differential I/O pairs, clocks, etc.

This also gave me a start for the schematic part design. I went as far as to automatically name all the pins, had differential I/O where I needed it, clock pins, the different supplies, and separated into the respective banks. I generated the schematic symbol using the I/O direction and @@@ (i forget what its called, whether the input is state, clock, inverted or not). I also separated each bank into separate sub-units, each with their respective supply pins.

This level would never have been possible by hand. Doing a reduced version of this might help you get better than you will find anywhere online.

@thepancake:

as promised, I'm attaching the ULP script file I used with EAGLE. It should be quite easy to use... just rename the file attached to this post to .ulp and run it from a library edit window of EAGLE.

@donq:

your script seems much more advanced :)

did you use EAGLE? are you going to make your script available to the public?

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@thepancake:

did you use EAGLE? are you going to make your script available to the public?

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Yes, this was for Eagle. This script wouldn't be of much use to others because it is highly customized to my particular use.

I looked extensively for packages before I realized that there is nothing even close to what I needed online.

Eagle does have a script or user program that will create a generic BGA package (I think it comes with the standard install, in the scr or ulp directories. If not, it's on their website). You just enter the number of rows and columns, pitch, and it will generate a plain vanilla package and a symbol with the pins in numerical order spaced around the sides of a single rectangular package. I consider this far, far short of what a schematic symbol should be.

That is why I had to make my own script. Even though the highly customized script I finally wound up with is completely useless to anyone else, the method I used is the only way that what I did was possible.

There are Excel spreadsheets available at the Altera site for all variations of their FPGA's. Starting from this almost eliminates the possibilities of assignment errors from doing it manually, especially with the huge variants. Excel functions can be used to compose a string for each line of the spreadsheet, including as much as you want to spend the time doing. Once you get it right for one line, block-copy down the entire columns and it does all the other pins for you.

I went through a number of variations before I got exactly what I wanted. Doing this by hand would have been impossible. And I know my pins are named/numbered correctly because they come straight from Altera's spreadsheet.

I can almost guarantee that you will not be able to find symbols online, except for maybe the simplest devices. These could be done by hand in the time it would take you to find them online, or you can generate them from the generic Eagle script. If you want anything beyond the stock single rectangle schematic symbol, you are certainly going to have to do it yourself. I'm completely convinced it is worth the effort.

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I have done something similar as well. Although, instead of starting from the pinout spreadsheet from Altera, I imported the fitter pin-out file into Excel.

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Excellent! You have Pads following the names you assigned in Quartus. I'm have Quartus following the signal names I assigned in Eagle. Same idea, different direction.

Using the Altera spreadsheet gave me all the power/gnd/and any unused signals, including NC and DNU pins. Not only did this keep my library editor happy, it also let me generate the entire footprint from the script.

I also figure that when I swapped pins in my schematic design to ease routing, this information will eventually make its way to Quartus.

So far, I can't quite get all the info into the pin assignment editor, but all the signal names are there. Hopefully, I'll figure out how to get direction and other information eventually. For now, I still do that manually.

Both of our ways still need some manual intervention, but it sure beats the full manual way of doing it.

Library screen-shot of my results.

Each bank is a separate 'gate' so that it can be included in the schematic pages separately. Some I have marked as diff I/O, others are GPIO. All the identically named power/ground pins are overlaid so that one schematic connection connects them all. (For this chip, there were almost 250 GND_D pins and lots of repeat power pins. I really didn't need to see them all on the schematic as long as the layout knows about them.)

There is more detail than shows here, when the part is added to a schematic, or edited in the library editor. Pin# s and such.

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Using the Altera spreadsheet gave me all the power/gnd/and any unused signals, including NC and DNU pins. Not only did this keep my library editor happy, it also let me generate the entire footprint from the script.

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The fitter pin-out file includes all pins including power, ground, configuration, etc.

What I like about these methods is not so much the time saved, but the confidence that the schematic pin out matches the Quartus project 100%. Although, the time saved is a very nice bonus.