FPGA packages for PCB design

Library screen-shot of my results.

Each bank is a separate 'gate' so that it can be included in the schematic pages separately. Some I have marked as diff I/O, others are GPIO. All the identically named power/ground pins are overlaid so that one schematic connection connects them all. (For this chip, there were almost 250 GND_D pins and lots of repeat power pins. I really didn't need to see them all on the schematic as long as the layout knows about them.)

There is more detail than shows here, when the part is added to a schematic, or edited in the library editor. Pin# s and such.