Altera_Forum
Honored Contributor
9 years agoFPGA LVDS bank VCCIO issue
In a custom board we created, it is required to use LVDS pins in two banks. I know that the VCCIO of the corresponding bank should be 2.5V. Unfortunately the VCCIO was connected to 3.3V instead of 2.5V by mistake.
Can LVDS still work? The bank has LVDS input data pin and input CLK and output data.