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Altera_Forum's avatar
Altera_Forum
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9 years ago

FPGA LVDS bank VCCIO issue

In a custom board we created, it is required to use LVDS pins in two banks. I know that the VCCIO of the corresponding bank should be 2.5V. Unfortunately the VCCIO was connected to 3.3V instead of 2....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

It will 'work' but won't conform to the timings specified in the datasheet. If you only have LVDS input signals then, perhaps, it will simply work as you hope. Output LVDS signals would be a different issue.

Either way - whether it appears to work or not - I recommend you correct the design error.

Cheers,

Alex