Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

FPGA LVDS bank VCCIO issue

In a custom board we created, it is required to use LVDS pins in two banks. I know that the VCCIO of the corresponding bank should be 2.5V. Unfortunately the VCCIO was connected to 3.3V instead of 2....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Is there no way of modifying the board such that you feed that bank with the right voltage?

LVDS output signals will simply be a little misshaped. Being a current based signalling standard, the IO circuitry - driven at 3.3V - will be able to drive the rising/falling edges faster. They're unlikely to damage the Cyclone IV and it will most likely just work. However, you will be operating your devices out of spec. So, Altera won't support you should you suddenly start burning out parts - something I think unlikely to happen but it's still a potential issue.

Cheers,

Alex