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Altera_Forum's avatar
Altera_Forum
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9 years ago

FPGA LVDS bank VCCIO issue

In a custom board we created, it is required to use LVDS pins in two banks. I know that the VCCIO of the corresponding bank should be 2.5V. Unfortunately the VCCIO was connected to 3.3V instead of 2....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

This FPGA (Cyclone 5 btw) will talk to another FPGA (Cyclone 4) through LVDS.

Will output LVDS signals be an issue?

Fixing the design will require few weeks for new board manufacturing. I was hoping to test the whole system first because there are other components, .....