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Altera_Forum's avatar
Altera_Forum
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9 years ago

FPGA LVDS bank VCCIO issue

In a custom board we created, it is required to use LVDS pins in two banks. I know that the VCCIO of the corresponding bank should be 2.5V. Unfortunately the VCCIO was connected to 3.3V instead of 2....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

The main problem is that the 3.3V is supplied to few other components and banks and I cannot just modify it. If I fed it with 2.5V, other FPGA banks may not be able to communicate with other chips.

I will try to reduce the voltage to 3V and try to power and test the system. I hope it works even for just testing. New boards should be designed later.

Thanks.