FPGA full reconfiguration using MAX II CPLD

This is the information provided in the user manual:

Configuration

This section describes the FPGA, flash memory, and MAX II CPLD System Controller

device programming methods supported by

the Stratix V GX transceiver signal

integrity development board.

The Stratix V GX transceiver signal integrity development board supports three

configuration methods:

■

Embedded USB-Blaster is the default method for configuring the FPGA at any

time using the Quartus II Programmer in

JTAG mode with the supplied USB cable.

■

MAX II and flash FPP download for configuring the FPGA using stored images

from the flash on either power-up or pressing the reset push-button (S5).

■

JTAG header (J93) for initial debugging an

d to bring up the on-board USB-Blaster

circuitry.

link: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/rm_svgx_si_dev_board.pdf

I don't think you've explained your question clearly enough. Pressing S5 - a push button - will cause the MAX II System Controller to reconfigure the FPGA.

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Is there a way to do it using the push button as documented in the user guide and reference manual ?

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S5 is a push button. So, is this not exactly what you want?

Cheers,

Alex

Hi Alex,

Actually, that is exactly what I want. The only problem is It doesn't work! I downloaded the MAX II RTL source code (kit installation : https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-transceiver-si-stratix-v.html) and the signal related to the push button is not even connected to the rest of the design.

The first thing I tried is to simply connect this signal to the reset generator module which generates the reset signal for the rest of the modules but I couldn't reconfigure the FPGA. Then I performed several modifications in other modules trying to use pfl_nreconfigure(pfl_control module) or srst (fgpa_interface <-> pfl_control modules) signals in order to perform this reset using the S5 push button but nothing worked.

Since the SRST button is disabled even in the Board Test System GUI I am wondering if it is even possible to perform this reconfiguration from the flash memory as documented in the user and reference manuals for the board.

Cheers,

Filip

I understand - and I agree. Button S5 does not appear to be connected in the System controller code - not the code that comes with the kit anyway.

Hooking 'nRESET' up to the reset generator block seems logical - but you say you've already tried that...? Just to be clear (and I apologise if this is teaching you to suck eggs), you changed line 321 [max_s5_si.vhd] to:

reset_in => nRESET,

I'm struggling to see why this doesn't work.

The quick start guide states:

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Reconfigure the FPGA with the new files by changing jumper J28 back to user position, then repowering your board or pushing RESET (S5) to reconfigure the FPGA.

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However, it's clear from the code included with the kit that S5 isn't even connected up.

So, I'd raise a ticket with Altera.

Cheers,

Alex

Hi Alex,

Thanks for the reply and don't worry, it doesn't sound as teaching me at all. That is the only way to solve the problem so please feel free to ask me whatever you find important.

Yes, that was the first thing I tried and I still couldn't perform the reconfiguration. I have a simple design running in the FPGA controling a pair of leds. When pressing the button (which is connected to the reset_generator in my version of the RTL) nothing happens and I find it impossible that a reconfiguration process so fast that I can't notice the leds turning off for at least a second.

Also, when pressing the button on board power up it seems that the configuration is not affected at all.

Thanks for the ticket. If you get the some results please let me know. Just take into account that just connecting reset_in => nRESET is not a solution to the problem.

Cheers,

Filip

Just to confirm - I suggest you raise a ticket with Altera. I won't be. I don't have this dev kit to try any fix on...

Cheers,

Alex

I took the "d" for "ll" somehow, sorry :)

When I get some feedback I'll post it here.