FPGA full reconfiguration using MAX II CPLD

Honored Contributor

10 years ago

This is the information provided in the user manual:

Configuration

This section describes the FPGA, flash memory, and MAX II CPLD System Controller

device programming methods supported by

the Stratix V GX transceiver signal

integrity development board.

The Stratix V GX transceiver signal integrity development board supports three

configuration methods:

■

Embedded USB-Blaster is the default method for configuring the FPGA at any

time using the Quartus II Programmer in

JTAG mode with the supplied USB cable.

■

MAX II and flash FPP download for configuring the FPGA using stored images

from the flash on either power-up or pressing the reset push-button (S5).

■

JTAG header (J93) for initial debugging an

d to bring up the on-board USB-Blaster

circuitry.

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