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I did set the power-on trigger in the SignalTap II instance , committed to FLASH, powered the system on and in the Signaltap session, tried to "Read Data" resulting in a message like trigger not seen.
As a sanity check, I changed the trigger to be the rising edge of the alive_led, recompiled , committed to FLASH and powered the system on. This time in the SignalTap session, the "Read Data " operation returns the trace buffer with the trigger condition at the center indicating the trigger was hit.
If this is a case of the FPGA still configuring when RST# at the slot is deasserted, I'm not even sure delaying POST will help.
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It certainly sounds like your FPGA is not configuring within the required time.
Did you review the board design, i.e., how is the board configuring now, and can it ever meet timing? It might only be possible to meet power-on timing using CvP mode.
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1. RST# may be required to initialize logic and it is never seen active when the FPGA logic is running.
As a confirmation, I would like to scope out the power ramp, RST# signal and the FPGA DONE signal or whatever indicated the FPGA is configed and running functional
clocks.
To test this , I figure I may be able to provide a local reset via a user switch so I can reset the FPGA manually. ( OR'ing the slot RST# with my on board reset )
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I have some notes on the timing requirements of PCIe;
http://www.ovro.caltech.edu/~dwh/wbsddc/ts4_power.pdf PCIe link negotiation is supposed to start after RST# deasserts, so if your board is too slow, it fails to enumerate.
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Altera has introducted CvP , in part I believe as the text below indicates ... past issues with power up timing vs FPGA configuration times.
"....Altera’s new device configuration mode—configuration via protocol (CvP)—can be
used with PCI Express® to configure the core fabric of Altera’s 28-nm Arria® V,
Cyclone® V, and Stratix® V FPGAs. CvP can reduce product cost and board size,
while simplifying the software usage model, and providing robust in-field system
upgrade capability. In addition, the autonomous, embedded PCIe IP core helps
ensure that designs meet PCIe power-up time requirements, irrespective of the FPGA
core fabric configuration time, guaranteeing a wide range of interoperability with
various PCIe-based computer platforms....."
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Yeah, that is the intention, but there are various errata for various chip revisions, so you'd have to see whether your board supports it.
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2. Could the Intel PCIe chipset enumerate the PCIe slots only once and then disabled the slot ?
To investigate this I figure I will call HP support to see if they know anything about it.
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Its possible to re-enumerate the PCIe bus after power-on, however, this method is complicated by the fact that if the PCIe BIOS does not find a device at power-on, any of the bridges between the and the root-complex device might not be configured (their address map window might be too small). I'm not sure how various OSes handle re-enumeration, and whether that includes changing the PCIe bridge windows.
Keep in mind that Altera does not guarantee that their boards meet any sort of requirements with regards to meeting PCIe timing. Many people use these boards, and simply live with the fact that you have to warm-boot to get the board visible over PCIe ... this is one of those implied disclaimers that come with the name "Development Kit".
Personally I'd recommend getting another PCIe motherboard. I use a OneStopSystems motherboard and a x1 PCIe Expresscard to use my laptop to interface to PCIe boards. Its not the highest bandwidth solution, but its completely independent of any development machines.
http://www.onestopsystems.com/pcie_atx_bp.php They also have an external PCIe enclosure (different web site name, but same company)
http://www.maxexpansion.com/ I haven't tried the cubes, they look cool though.
Cheers,
Dave
Honored Contributor
