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Altera_Forum
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13 years ago

FPGA configuration time and PCIe secification

Has anyone used the PCIe interface of a Cyclone device while configuring it using the AS (active serial) scheme? I'm using a Cyclone IV device (EP4CGX30F484) and planning to use its PCIe interf...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanks dwh ...

I was able to ge the Signaltrap into the design and have it trigger. The ltssm seems to be cycling through states 0, 1 and 2.

I still need to add the RST# signal ... included and the Windows 7 seems to take the power supplies down on a restart ... I have tried to check

the POST / BIOS for a configuration to disable this but have not found one.

I have tried to interrupt the POST / BIOS but it didn't seem to make any difference ...

I believe I need to configure the Signaltrace to FLASH to see if I can capture the rising edge of RST#

Otherwise I will need to check the rising edge of RST# and the signal indicating the FPGA is configured and running.