FPGA configuration time and PCIe secification

Might be worth trying to load a very minimal fpga image - maybe little more than a single PCIe BAR connected to an M9K block.

Another problem I've not seen a solution to is how to select a 'factory' image when using CvP, especialy if using AS to load the periphery image.

There almost certainly isn't time to load a small image from the start of the EPCS which then determines whether to reload using either a 'factory' or 'user' image.

If PS is used you can use a jumper to select the EPCS offset - not ideal, but better than having to use JTAG.

Without that you always need the rest of the image in order to program a different one.