Honored Contributor
Honored ContributorDave some random thoughts.
1. If I could isolate the +3.3 V and +12V PCIe slot power using a riser card, I could power the development card with its external ( brick ) power source. This way it would be up and running when the slot gets reset .. 2. I need a POST / BIOS setting to delay the PCIe slot reset and enumeration but have not found such a delay ... the BIOS delay I set to 30 seconds today and it didn't help 3. For some reason, when the card is installed and I run PCIscope that is a utility to display the PCI configuration, a bus 02 shows up with nothing in it. If I force the bus 02, 00, 00 device to display resisters they are all F's and sometimes a Master Abort error is reported. I', thinking bus 02 must be a function of the present ( prst# ) being active . There is a X1, X4 and X8 I think and they say something about the card width capabilities. The wierd thing is they are souced by the FPGA and I would think they would be TRI-state until the FPGA is configured. Tomorrow I will set the switch to isolate all 3 signals from the FPGA to see what happens. 4. I am still stumped on getting the system to "warm start" which I expect to be a start from the begining of POST but with the power not cycled. This HP system seems to want to re cycle the power from off for restart and I don't want it to. Thanks for your help ... it seems the development card , is a good candidate in this system to do some debugging when we thought it would be a cake walk ! I
