Honored Contributor
Honored ContributorCan anyone help with this related question ... I have a DK-DEV-5SGXEA7N which is the Stratix V FPGA development kit running the example PCIe designs hip_s5gx_x1_g2_ast64_5SGXEA7K2F40_121SP1.qar
The host system is a HP Z220 deskside system with various PCIe slots. To date , I have not been successful in getting the development card recognized or the altpci_demo_63 application to see the card. I have tried various lane sized and stuck to Gen2 speed. I need a X1 -> X16 riser card to be able to try the X1 slots. I believe the card worked fine in another PCIe system and am wondering if there is some race between the training and the BIOS comming up ? I have tried to stall the BIOS by interrupting it , but would,need to probe further to see if the Intel chipset is trying to train while the FPGA is still configuring. Once Windows 7 is up I have run several utilities that probe the PCIe slots, and I believe the utility says the slot is seen as having something in it by the present pin, but says the bus02 is empty. Asking the utility, PCIscope, to read the slot comes up with all F's for all registers and sometines an error "Master Abort". One other thing, the 4 lane LEDS on the top of the card user_LED[4..7], I have seen all come on then, when I continued BIOS, one led went out. Also user LED[0] someties appears to have both gren and red on together . Any ideas as this is a loaner card and I can't make much progress if the application program can't see the card . I was able to modify the alive_led flash rate indicating the system could re-build and get the FLASH re-programmed.
