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Altera_Forum
Honored Contributor
Honored ContributorFPGA Configuration problem using Flash Memory
Hi All,
I am trying to configure my FPGA through Flash memory. Though my flash memory is getting programmed successfully, the fpga is not getting configured. Can anyone suggest me what could be the possible reasons for this. I am using Quartus II 6.1 version. FPGA is Stratix II GX - ep2s90ff1508c3 MAX II device - epm570gt100c3n JTAG chain for programming procedure followed: 1) Made a project with MAX II device. 2) Generated the MegaCore function "Parallel Flash Loader" combined for Programming and Configuration. 3) In programming window added the PFL pof. 4) In that added my CFI_512 flash device. 5) Now added my design file pof (flash format) to this CFI_512 flash. my design file pof is for Stratix II GX device. In that i generated a new pof for flash device. 6) Programed through JTAG. Please suggest. Thank you, -Amit29 Replies
Altera_ForumI don't know what could be wrong, but I can give you some hint.
Can you see the conf_done LED (D8) switched ON after pressing S1 ? (It is a green LED near the S1 button.) Did you consider that when the S6 is switched 'ON', it actually pulls down the appropriate signal ? That is, 'ON' position means logic '0' ! If it is still not working, I will detail the procedure, which works for me...- Altera_Forum
Could you kindly send me ur whole procedure along with each minute details of it and the the settings of ur s6 switch. or u can mail me
[email protected] waiting for ur reply :) - Altera_Forum
I try to attach a short note with the details. I hope it helps you or anybody else. Good luck!
- Altera_Forum
:) A hearty thanks to csaba. But the sad part is i'm still not able to configure the fpga.:o
I have quartusII6.1 fullversion. I tried the procedure given by u , using it. Then i shifted to quartusII7.2 web edition, but couldn't get the desired result. Can u tell something about the PFL generated by U and it's pin assignment. Do we need to take care espcially, any pin ? I have just mapped the pins of my PFL to the MAX II pins as mentioned in user guide. or Can u send ur project file. That could be of greta help. regards, - Altera_Forum
Hi,
actually, you don't have to worry about the PFL project assignments, as long as you are using the one, which is delivered with the kit. If you install the CD, which was included in the kit, you should be able to find the archive of the original project under: C:\altera\Kits\SIIGX_PCIe_Kit-v1.0.1\Examples\ManufacturingTestDesigns\pfl2.qar The only reason to modify this project was that the PFL macro had to be upgraded from v2 to v3 (see one of my previous posts). - Altera_Forum
hi ,
Actually i too faced the same problem of version . In ref. to ur prev comment,where u have mentioned about generating a new PFL using quartus 8.0V . There u might be assigning the pins of MAX to Stratix. I was reffering to those assignments. anyway i have used the PFL.qar to generate the project and tried to configure it but in vain .:o :o :o U keep on referring factory default config, and factory deafult SOF what does that refer to ? Anyway I am trying with all possible ways of configuring it... Hearty thanks for ur efforts - Altera_Forum
Can anybody tell me about the factory default config or factory default SOF , ?????:confused:
- Altera_Forum
Hi,
first of all, when you change the version of the PFL, you don't have to worry about the assignments, as long as you are using the original Quartus II project. This will guarantee that all the assignments are inherited properly. If you install the development kit CD at the default location, you will find the factory default project and other useful files under: C:\altera\Kits\SIIGX_PCIe_Kit-v1.0.1\Examples\ManufacturingTestDesigns I use the s2gx_pcie_top as the reference design. Cheers, - Altera_Forum
hi Csaba,
I have few doubt . Can i have ur number to call u personally?:) - Altera_Forum
Hi ....... Thanx a lot Csaba for all the help and guidance ...... things are working for me now :)
Cheers.
