Forum Discussion
Honored ContributorFPGA architecture
Hi all,
I'm starting a new project and I need some help with the FPGA architecture. The concept is very simple - the FPGA will sample an input parallel bus (24 or 48 signals @ 150MHz max) and stream it down a PCIe bus. The FPGA will use an external IP for the PCIe bus, combined with Altera's hard IP. The input bus uses its own clock (meaning that the FPGA is the slave for that matter). The FPGA will be probably Cyclone IV. My questions are: 1. Which oscillator frequency should I use for the basic FPGA clock (use a high frequency oscillator or use something like 50MHz and then a PLL to boost it)? 2. How do I make the connection between the FPGA internal clock and the bus clock? For a slow bus clock I would usually register it with 3-4 flip-flops but since this clock is at 150MHz I'm not sure that it the the best solution since I can't oversample it too much. 3. While transferring the data from the FPGA IOs to the PCIe transceiver, is it mandatory to use pipelining? If so what is the best way to do that? Thank you11 Replies
Altera_Forum1. Whats wrong with the bus clock?
2. use a dual clock fifo (DCFIFO in the megafunctions library) 3. It depends what interface the core is using. You have the choice of two Avalon interfaces, Streaming or Memory mapped. Im not up to speed on MM interfaces, but for streaming you need to construct the top level packets (ie put a header on the the data) before putting it into a FIFO, so yes, pipelineing is probably required. I suggest you get reading the documentation for the PCIe core - its not that straight forward.- Altera_Forum
1. The bus isn't working all the time. The FPGA has a few more things to do so I need another clock
2. Got it. 3. The core uses Avalon ST 64 or 128-bit interface. Which one is better to use in my case? Where can I find a reference or an example of the pipelining usually used in such designs? - Altera_Forum
You'll have to see what the cyclone supports. I suspect it will only be the 64-bit interface, but best way to find out is generate a core using the megawizard.
- Altera_Forum
Generate which core? When I said external core, I meant a core that I'll purchase from an external vendor (I'm thinking about plda but I'm open for suggestions), so I can't generate it with the megawizard.
- Altera_Forum
As far as I'm aware of, the Altera PCIe core is originated from PLDA. So why don't you want to use the Altera core, or at least the evaluation version for test?
O.K., if you are going for PCIe with external PHY, which is only offered by PLDA directly, you'll need to refer to PLDA. But didn't you say Altera Hard IP? Then you would use the free Altera Megafunction. - Altera_Forum
I didn't know that. The thing is that I need to transfer a lot of data (about 6.5Gbps) and the local Altera representative recommended to purchase PLDA's IP. They also sell the windows driver so I need that anyway. I assume that I won't achieve the same performance using only the Altera core? Do you know whether the core itself is similar to PLDA's core or is it completely different (inputs, clocks etc.)? Is there an application that I can use with Altera's core in order to stream data to a PC and test the PCIe throughput?
- Altera_Forum
I was under the impression that PLDA provided the soft core and Altera provided the hard core.
- Altera_Forum
The PCIe IP cores, either from PLDA or Altera, are quite expensive. Saving the invest and hopefully FPGA resources and compilation time are main motivations to go for hard IP.
A 4-lane Cyclone IV GX PCIe interface has a nominal throughput of 8 GBPS. - Altera_Forum
I am under the same impression as Tricky - as I see it PLDA's soft IP optimizes Altera's hard IP.
Could you guys refer to my second question - how do I connect the bus clock to the FPGA main clock? - Altera_Forum
I already suggested a DCFIFO.
