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Altera_Forum
Honored Contributor
Honored ContributorFPGA architecture
Hi all, I'm starting a new project and I need some help with the FPGA architecture. The concept is very simple - the FPGA will sample an input parallel bus (24 or 48 signals @ 150MHz max) and stre...
Altera_ForumHonored Contributor
Honored Contributor1. The bus isn't working all the time. The FPGA has a few more things to do so I need another clock
2. Got it. 3. The core uses Avalon ST 64 or 128-bit interface. Which one is better to use in my case? Where can I find a reference or an example of the pipelining usually used in such designs?
