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Altera_Forum
Honored Contributor
Honored ContributorFPGA architecture
Hi all, I'm starting a new project and I need some help with the FPGA architecture. The concept is very simple - the FPGA will sample an input parallel bus (24 or 48 signals @ 150MHz max) and stre...
Altera_ForumHonored Contributor
Honored ContributorI am under the same impression as Tricky - as I see it PLDA's soft IP optimizes Altera's hard IP.
Could you guys refer to my second question - how do I connect the bus clock to the FPGA main clock?
