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Altera_Forum
Honored Contributor
Honored ContributorFPGA architecture
Hi all, I'm starting a new project and I need some help with the FPGA architecture. The concept is very simple - the FPGA will sample an input parallel bus (24 or 48 signals @ 150MHz max) and stre...
Altera_ForumHonored Contributor
Honored Contributor1. Whats wrong with the bus clock?
2. use a dual clock fifo (DCFIFO in the megafunctions library) 3. It depends what interface the core is using. You have the choice of two Avalon interfaces, Streaming or Memory mapped. Im not up to speed on MM interfaces, but for streaming you need to construct the top level packets (ie put a header on the the data) before putting it into a FIFO, so yes, pipelineing is probably required. I suggest you get reading the documentation for the PCIe core - its not that straight forward.
