Honored ContributorHi all.
I'm using FIR compiler II megafunction to create a block with the following parameters: Decimation filter this N = 2; Number of channels : 11; Clock frequency : 50 MHz; Input sample rate : 0.12 MHz; I have got new input ports: ast_sink_sop and ast_sink_eop. Sometimes i want to send data only to the channel number 1 and don't use other channels. How can I do it?
Honored Contributorif you don't need any channel just ignore it. its input becomes irrelevant and you will discard its output. You need however (I believe) keep valid same for all cases since the core expects 11 valid data per its cycle.
Honored ContributorI have a few cases:
1. Use all channels : Valid is '1' all 11 cycles SoP is '1' only then send data of 0 channel EoP is '1' only then send data of 10 channel 2. Use only 3 channels Valid is '1' all 11 cycles SoP is '1' only then send data of 0 channel EoP is '1' only then send data of 2 channel Am I right? 3. Use only 1 channel Valid is '1' all 11 cycles SoP is '1' only then send data of 0 channel When I should use EoP?Honored Contributoryour valid is ok.
your SOP,EOP what are these? I assume some start/end of some frames. If you are filtering then I don't know what frames mean here. Can you explain it please?Honored ContributorIn my filter Input sample rate much less than Clock frequency, thats why all 11 channels can pass through 1 wire.
Filter characteristics: PhysChanIn 1, PhysChanOut 1, ChansPerPhyIn 12, ChansPerPhyOut 12, OutputFullBitWidth 58, Bankcount 1, CoefBitWidth 20 In this case we have Start of packet and End of packet wires. (http://www.altera.com/literature/ug/ug_fir_compiler_ii.pdf Table 4–2 page 4–23) Better picture of how it works is Figure 4–5.Honored ContributorFIR Compiler II's architecture is such that it always expects the same input pattern. So if you've created an 11-channel FIR filter but are only interested in 1 channel then you will need to pad the inputs with 10 dummy samples and then just ignore the corresponding outputs. Fairly certain EOP should always be asserted on the 11th channel.
Honored ContributorHonored ContributorThanks all of you.
So, valid and sop/eop signals: valid high - all 11 cycles sop high - only 1 cycle eop high - only 11 cycle. Is this true? And what about dummy samples? I think that i can't send dummy samples, because this will fake results. It seems that there is no solution of this problem.Honored ContributorHonored ContributorWhen I said dummy samples I mean you just assert valid and it doesn't matter what value goes on the input at that point. It will produce "fake" results, but it doesn't matter as you will only be selecting the results from the channels you care about.
Honored ContributorI didn't describe the problem, my fault.
I have 11 fir filters connected in series, each with decimation factor = 2, clock frequence = 120 kHz,same coefficients and different input sample rates (because of the decimation): 1. 120 kHz 2. 60 kHz 3. 30 kHz 4. 15 kHz 5. 7500 Hz 6. 3750 Hz 7. 1875 Hz 8. 937,5 Hz 9. 468,75 Hz 10. 234,375 Hz 11. 117,1875 kHz It's working, but can't fit in our FPGA, even in case of increasing clock frequence. Thats why I want to do it with one filter and 11 channels. So, I want to use this channels with different frequences. I hope I explained the problem clear. What do you think about it?
