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In my filter Input sample rate much less than Clock frequency, thats why all 11 channels can pass through 1 wire.
Filter characteristics: PhysChanIn 1, PhysChanOut 1, ChansPerPhyIn 12, ChansPerPhyOut 12, OutputFullBitWidth 58, Bankcount 1, CoefBitWidth 20
In this case we have Start of packet and End of packet wires.
(
http://www.altera.com/literature/ug/ug_fir_compiler_ii.pdf Table 4–2 page 4–23)
Better picture of how it works is Figure 4–5.
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I am used to dspBuilder fir design and in such cases no sop or eop exists as the fir core depends on valid for counting channels thus it will just count on valid from 0 to 10 for 11 channels and at next valid the count resets to 0 and so on.
It looks like fir compiler you are using needs valid as well as sop/eop as you know.
I believe since your design expects 11 channels then this is fixed and so sop/eop must be fixed irrespective of channels actually used. It will be safer to assume 11 channels and discard those you don't need.
but I could be wrong if your design can actually accommodate to any channels from 1 to 11 though it is set to 11.
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