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Altera_Forum
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12 years ago

FIR Compiler II multichannel operation

Hi all. I'm using FIR compiler II megafunction to create a block with the following parameters: Decimation filter this N = 2; Number of channels : 11; Clock frequency : 50 MHz; Input...
Altera_Forum's avatar
Altera_Forum
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12 years ago

I didn't describe the problem, my fault.

I have 11 fir filters connected in series, each with decimation factor = 2, clock frequence = 120 kHz,same coefficients and different input sample rates (because of the decimation):

1. 120 kHz

2. 60 kHz

3. 30 kHz

4. 15 kHz

5. 7500 Hz

6. 3750 Hz

7. 1875 Hz

8. 937,5 Hz

9. 468,75 Hz

10. 234,375 Hz

11. 117,1875 kHz

It's working, but can't fit in our FPGA, even in case of increasing clock frequence.

Thats why I want to do it with one filter and 11 channels.

So, I want to use this channels with different frequences.

I hope I explained the problem clear. What do you think about it?