Filter & decimation implementation on AD7401

The original Verilog code is an example of bad coding style, involving word_clk designed as a ripple clock, but it's basically working.

  if mdata1='1' then
    ip_data1 <= ip_data1 + '1';
  else 
    ip_data1 <= ip_data1 - '1';

Can you explain to us how that is expressed in VHDL?

ip_data1 <= 1;

DELTA1 <= DELTA1 + 1;

ip_data1 <= conv_std_logic_vector(1,24);

Ok, we tried to merge in some way the code of ADS1202 and AD7401, and we got really great results of the code which came out.

The results are correct, except for the unhandled arithmetic overflow with mdata = '1'. I suggest to consider it in the code.

  if CN5(24) = '1' then
    DATA(15 downto 0) <= (others => '1');
  else  
    DATA(15 downto 0) <= CN5(23 downto 8);
  end if;

FvM thank you we corrected that, although we had tried that out, but in a different way!

In addition, I see a timing violation in my compilation, caused by the previously mentioned ripple clock. Implementing word_clk as a clock enable removes this problem.

FvM, I tried to implement it as a clock_enable, but results were terrible!

process(clk20,reset)
begin
  if reset = '0' then
    clk_en <= '0';
  elsif clk20'event and clk20 = '0' then
    cnt <= cnt + 1;				-- cnt is a 8-bit vector
    if cnt(7) = '1' then
      clk_en <= NOT(clk_en);
    end if;
  end if;
end process;

A clock enable should be active for one clock cycle, e.g.:

process(word_count)
begin
 if word_count = x"ff" then 
  word_clk <= '1';
 else
   word_clk <= '0';  
 end if;
end process;

 if reset = '0' then
  --
 elsif clk20'event and clk20 = '1' then
  if word_clk = '1' then 
    DN0 <= CN2;
    --
  end if;
 end if;

Ok FvM I did that and it works great!

process(clk20,reset)
begin
  if reset = '0' then
    DATA <= (others => '0');
  elsif clk20'event and clk20 = '1' then
    if word_clk = '1' then
      if CN5(24) = '1' then
        DATA(15 downto 0) <= (others => '1');
      else  
        DATA(15 downto 0) <= CN5(23 downto 8);
      end if;
    end if;
  end if;
end process;