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Honored Contributor
Honored ContributorFilter & decimation implementation on AD7401
Hello everybody! We have chosen the AD7401 Sigma Delta modulator for our project, translated the Verilog code given by the datasheet into VHDL and are now confused about the results of the simu...
Altera_ForumHonored Contributor
Honored ContributorFvM, I tried to implement it as a clock_enable, but results were terrible!
process(clk20,reset)
begin
if reset = '0' then
clk_en <= '0';
elsif clk20'event and clk20 = '0' then
cnt <= cnt + 1; -- cnt is a 8-bit vector
if cnt(7) = '1' then
clk_en <= NOT(clk_en);
end if;
end if;
end process;
