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Altera_Forum
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16 years ago

Filter & decimation implementation on AD7401

Hello everybody! We have chosen the AD7401 Sigma Delta modulator for our project, translated the Verilog code given by the datasheet into VHDL and are now confused about the results of the simu...
Altera_Forum's avatar
Altera_Forum
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16 years ago

FvM, I tried to implement it as a clock_enable, but results were terrible! 

process(clk20,reset)
begin
  if reset = '0' then
    clk_en <= '0';
  elsif clk20'event and clk20 = '0' then
    cnt <= cnt + 1;				-- cnt is a 8-bit vector
    if cnt(7) = '1' then
      clk_en <= NOT(clk_en);
    end if;
  end if;
end process;

After that I used clk_en in combination with the system clock directly in the processes where word_clk used to be.

Could you please suggest to me some other way of implementing that?