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Altera_Forum's avatar
Altera_Forum
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16 years ago

Filter & decimation implementation on AD7401

Hello everybody! We have chosen the AD7401 Sigma Delta modulator for our project, translated the Verilog code given by the datasheet into VHDL and are now confused about the results of the simu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The results are correct, except for the unhandled arithmetic overflow with mdata = '1'. I suggest to consider it in the code. 

  if CN5(24) = '1' then
    DATA(15 downto 0) <= (others => '1');
  else  
    DATA(15 downto 0) <= CN5(23 downto 8);
  end if;