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Altera_Forum
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16 years ago

Filter & decimation implementation on AD7401

Hello everybody! We have chosen the AD7401 Sigma Delta modulator for our project, translated the Verilog code given by the datasheet into VHDL and are now confused about the results of the simu...
Altera_Forum's avatar
Altera_Forum
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16 years ago

In addition, I see a timing violation in my compilation, caused by the previously mentioned ripple clock. Implementing word_clk as a clock enable removes this problem.