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Altera_Forum's avatar
Altera_Forum
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16 years ago

Filter & decimation implementation on AD7401

Hello everybody! We have chosen the AD7401 Sigma Delta modulator for our project, translated the Verilog code given by the datasheet into VHDL and are now confused about the results of the simu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

A clock enable should be active for one clock cycle, e.g.: 

process(word_count)
begin
 if word_count = x"ff" then 
  word_clk <= '1';
 else
   word_clk <= '0';  
 end if;
end process;

and 

 if reset = '0' then
  --
 elsif clk20'event and clk20 = '1' then
  if word_clk = '1' then 
    DN0 <= CN2;
    --
  end if;
 end if;