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Altera_Forum's avatar
Altera_Forum
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16 years ago

Filter & decimation implementation on AD7401

Hello everybody! We have chosen the AD7401 Sigma Delta modulator for our project, translated the Verilog code given by the datasheet into VHDL and are now confused about the results of the simu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The original Verilog code is an example of bad coding style, involving word_clk designed as a ripple clock, but it's basically working.

You have confused the code by an adder, that hasn't been there before and apparently act's as a kind of random number generator in your simulation. 

  if mdata1='1' then
    ip_data1 <= ip_data1 + '1';
  else 
    ip_data1 <= ip_data1 - '1';

The purpose of this combinational code is to assign 0/+1 respectively -1/+1 to ip_data1, not to sum up anything.