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Altera_Forum
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16 years ago

Filter & decimation implementation on AD7401

Hello everybody! We have chosen the AD7401 Sigma Delta modulator for our project, translated the Verilog code given by the datasheet into VHDL and are now confused about the results of the simu...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Can you explain to us how that is expressed in VHDL? 

ip_data1 <= 1;

Because, for instance, in SBAA094 of ADS1202 it is done the way we did it. 

DELTA1 <= DELTA1 + 1;

Where exactly is our code mistaken, despite the fact that it is bad coding style given by the datasheet itself. Shouldn't vector ip_data1 work as an adder?