Honored ContributorHi, I want to create 2 external LVDS clock signals to clock 2 ADC chips. I use a EP3C16Q240 device. According to the datasheet I have to use LVDS_e_3r solution, since the PLL Outputs are placed at the Top and Bottom pins of the Device, while true LVDS Transmitters are only supported at the Left and Right pins. How close should these resistors be placed to the FPGA transmitter pins?
Honored ContributorYou should place the resistors as close to the transmitter pins as possible.
Bent regards, BenHonored ContributorIf phase noise is an issue, you shouldn't clock fast ADCs through the FPGA. The jitter of the contributed by the FPGA clock path and PLL will be considerably higher than the crystal and ADC jitter.
Honored ContributorThank you ppl for your replies. The clocks will run at 320 MHz. Is this ok or should I use an external clock generation/distribution chip?
Honored ContributorCyclone III dedicated clock outputs can handle > 400 MHz clock signals. But according to the datasheet with a maximum peak-to-peak jitter of 300 ps. The aperture jitter of a good ADC can be expected about two orders of magnitude lower. It matters depending on the purpose of digitized signals.
