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Altera_Forum
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14 years ago

Emulated LVDS Resistors Placement

Hi, I want to create 2 external LVDS clock signals to clock 2 ADC chips. I use a EP3C16Q240 device. According to the datasheet I have to use LVDS_e_3r solution, since the PLL Outputs are placed at th...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Cyclone III dedicated clock outputs can handle > 400 MHz clock signals. But according to the datasheet with a maximum peak-to-peak jitter of 300 ps. The aperture jitter of a good ADC can be expected about two orders of magnitude lower. It matters depending on the purpose of digitized signals.