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Altera_Forum
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14 years ago

Emulated LVDS Resistors Placement

Hi, I want to create 2 external LVDS clock signals to clock 2 ADC chips. I use a EP3C16Q240 device. According to the datasheet I have to use LVDS_e_3r solution, since the PLL Outputs are placed at th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thank you ppl for your replies. The clocks will run at 320 MHz. Is this ok or should I use an external clock generation/distribution chip?