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Honored Contributor
Honored ContributorEmulated LVDS Resistors Placement
Hi, I want to create 2 external LVDS clock signals to clock 2 ADC chips. I use a EP3C16Q240 device. According to the datasheet I have to use LVDS_e_3r solution, since the PLL Outputs are placed at th...
Altera_ForumHonored Contributor
Honored ContributorIf phase noise is an issue, you shouldn't clock fast ADCs through the FPGA. The jitter of the contributed by the FPGA clock path and PLL will be considerably higher than the crystal and ADC jitter.
