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yairs's avatar
yairs
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2 years ago
Solved

E-Tile Hard IP for Ethernet pin placement

Hi.

I am trying to build a 100GE Interface for a stratix10 tx device(1st280ey2f55i2lg). I have compiled successfully the example design, but I do not know how to change the location of the e-tile in order to match it to my board. The example design uses :

set_location_assignment PIN_REFCLK_GXER9C_CH1P -to i_clk_ref
set_location_assignment PIN_GXER9C_TX_CH0P -to o_tx_serial[0]
set_location_assignment PIN_GXER9C_TX_CH1P -to o_tx_serial[1]
set_location_assignment PIN_GXER9C_TX_CH2P -to o_tx_serial[2]
set_location_assignment PIN_GXER9C_TX_CH3P -to o_tx_serial[3]
set_location_assignment PIN_GXER9C_RX_CH0P -to i_rx_serial[0]
set_location_assignment PIN_GXER9C_RX_CH1P -to i_rx_serial[1]
set_location_assignment PIN_GXER9C_RX_CH2P -to i_rx_serial[2]
set_location_assignment PIN_GXER9C_RX_CH3P -to i_rx_serial[3]

and when I try to change it to any other tile, I am getting a fitter error. I couldn't find what are the restrictions for the e-tile selection. Please help.

Thanks

yair shapira

Board Debug
Configuration
Other Ips
  • ZiYing_Intel's avatar
    ZiYing_Intel
    2 years ago

    Hi yair,

    It was the wrong pin assignment issue. You put 2 different signal in the same pin because you already

    set_location_assignment PIN_REFCLK_GXER9C_CH1P -to i_clk_ref. For further information about E-tile hard IP, you may refer to link below https://www.intel.com/content/www/us/en/docs/programmable/683468/21-1/introduction.html

    Since your issue has been resolved, I am now close the case. If you happen another issue after the case closed, please do feel free to submit another issue. There will have people reach out to you.

    Best regards,

    zying


9 Replies

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi yair shapira,


    May I know that you try change to which tile?


    Best regards,

    zying


  • yairs's avatar
    yairs
    Icon for New Contributor rankNew Contributor
    2 years ago

    Sure. Thanks for your help.

    I tried (among other options that I do not remember ..) To move to tile 8B channels 0 - 3.

    Yair,

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi yairs,


    Can you share the .qar file? So that I can try debug the issue from my side.


    Best regards,

    zying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Yairs,


    Can you try achieve the project again? because the file that you share to me corrupted and don't have the .qsf and .qpf file inside it.


    Best regards,

    zying


    • yairs's avatar
      yairs
      Icon for New Contributor rankNew Contributor
      2 years ago

      Thanks a lot , Now it compiles.

      I saw that you made a change in one of the TBI Clocks placement. Could you please elaborate (or refer me to some document) , what is the usage of the TBI Clocks and what are their pin placement rules.

      I am going to try to add at least one more 100GE ETILE IP, and probably some 10GE Interfaces in the future.

      Thanks for all your help

      yair

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi yair,

    It was the wrong pin assignment issue. You put 2 different signal in the same pin because you already

    set_location_assignment PIN_REFCLK_GXER9C_CH1P -to i_clk_ref. For further information about E-tile hard IP, you may refer to link below https://www.intel.com/content/www/us/en/docs/programmable/683468/21-1/introduction.html

    Since your issue has been resolved, I am now close the case. If you happen another issue after the case closed, please do feel free to submit another issue. There will have people reach out to you.

    Best regards,

    zying