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yairs's avatar
yairs
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2 years ago
Solved

E-Tile Hard IP for Ethernet pin placement

Hi. I am trying to build a 100GE Interface for a stratix10 tx device(1st280ey2f55i2lg). I have compiled successfully the example design, but I do not know how to change the location of the e-tile in...
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  • ZiYing_Intel's avatar
    ZiYing_Intel
    2 years ago

    Hi yair,

    It was the wrong pin assignment issue. You put 2 different signal in the same pin because you already

    set_location_assignment PIN_REFCLK_GXER9C_CH1P -to i_clk_ref. For further information about E-tile hard IP, you may refer to link below https://www.intel.com/content/www/us/en/docs/programmable/683468/21-1/introduction.html

    Since your issue has been resolved, I am now close the case. If you happen another issue after the case closed, please do feel free to submit another issue. There will have people reach out to you.

    Best regards,

    zying


ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi yairs,

I have a look and tried your .qar file from my side. It was the pin assignment issue. I made some changes on the pin assignment and it was compiled successfully from my side.

  • yairs's avatar
    yairs
    Icon for New Contributor rankNew Contributor
    2 years ago

    Thanks a lot , Now it compiles.

    I saw that you made a change in one of the TBI Clocks placement. Could you please elaborate (or refer me to some document) , what is the usage of the TBI Clocks and what are their pin placement rules.

    I am going to try to add at least one more 100GE ETILE IP, and probably some 10GE Interfaces in the future.

    Thanks for all your help

    yair