Dual-port access avalon memory simulation problem

Question

Hello,  I have created an Avalon dual access on-chip memory in Qsys and tried to simulate it, with success, everything worked just fine. Then I put this module in a VHDL component, and did nothing, just led out the signals without changing. Now when I simulate it, it throws me the error message below(ERROR_1). It says that it is suppressible, so I tried to suppress it, and it returns me the error message below(ERROR_2). It is really weird, as when I look at the altsyncram component in the RTL viewer, the data_a port is clearly 32 bits wide, as should be(see picture attached). A picture of the component is also attached.  What I am trying to do is to have a memory with read and write access from one port(gonna connect it later to the PCIe megafunction), and one port with read access from the application layer. I have seen some code interfacing a memory to the application layer, but it wasn't in any way simpler than mine, and I suppose just leading out ports should work.  Thanks, Tibor  ERROR_1: # ** Error (suppressible): (vsim-10000) /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v(103): Unresolved defparam reference to 'the_altsyncram' in the_altsyncram.address_reg_b.#     Time: 0 ps  Iteration: 0  Instance: /tau2_temp_calculate_tb/tau2_temp_calculate_inst/temp_table_inst/onchip_memory2_0 File: /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v#  ** Error (suppressible): (vsim-10000) /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v(104): Unresolved defparam reference to 'the_altsyncram' in the_altsyncram.byte_size.#     Time: 0 ps  Iteration: 0  Instance: /tau2_temp_calculate_tb/tau2_temp_calculate_inst/temp_table_inst/onchip_memory2_0 File: /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v#  ** Error (suppressible): (vsim-10000) /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v(105): Unresolved defparam reference to 'the_altsyncram' in the_altsyncram.byteena_reg_b.#     Time: 0 ps  Iteration: 0  Instance: /tau2_temp_calculate_tb/tau2_temp_calculate_inst/temp_table_inst/onchip_memory2_0 File: /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v#  ** Error (suppressible): (vsim-10000) /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v(106): Unresolved defparam reference to 'the_altsyncram' in the_altsyncram.indata_reg_b.#     Time: 0 ps  Iteration: 0  Instance: /tau2_temp_calculate_tb/tau2_temp_calculate_inst/temp_table_inst/onchip_memory2_0 File: /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v#  ** Error (suppressible): (vsim-10000) /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v(107): Unresolved defparam reference to 'the_altsyncram' in the_altsyncram.init_file.#     Time: 0 ps  Iteration: 0  Instance: /tau2_temp_calculate_tb/tau2_temp_calculate_inst/temp_table_inst/onchip_memory2_0 File: /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v#  ** Error (suppressible): (vsim-10000) /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v(108): Unresolved defparam reference to 'the_altsyncram' in the_altsyncram.lpm_type.#     Time: 0 ps  Iteration: 0  Instance: /tau2_temp_calculate_tb/tau2_temp_calculate_inst/temp_table_inst/onchip_memory2_0 File: /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v#  ** Error (suppressible): (vsim-10000) /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v(109): Unresolved defparam reference to 'the_altsyncram' in the_altsyncram.maximum_depth.#     Time: 0 ps  Iteration: 0  Instance: /tau2_temp_calculate_tb/tau2_temp_calculate_inst/temp_table_inst/onchip_memory2_0 File: /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v#  ** Error (suppressible): (vsim-10000) /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v(110): Unresolved defparam reference to 'the_altsyncram' in the_altsyncram.numwords_a.#     Time: 0 ps  Iteration: 0  Instance: /tau2_temp_calculate_tb/tau2_temp_calculate_inst/temp_table_inst/onchip_memory2_0 File: /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v
.
.
.  ERROR_2 # ** Warning: (vsim-8822) /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v(85):  - Missing Verilog connection for formal VHDL port 'rden_a'.#     Time: 0 ps  Iteration: 0  Instance: /tau2_temp_calculate_tb/tau2_temp_calculate_inst/temp_table_inst/onchip_memory2_0/the_altsyncram File: /home/work/intelFPGA_lite/16.1/modelsim_ase/linuxaloem/../altera/vhdl/src/altera_mf/altera_mf.vhd#  ** Warning: (vsim-8822) /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v(85):  - Missing Verilog connection for formal VHDL port 'rden_b'.#     Time: 0 ps  Iteration: 0  Instance: /tau2_temp_calculate_tb/tau2_temp_calculate_inst/temp_table_inst/onchip_memory2_0/the_altsyncram File: /home/work/intelFPGA_lite/16.1/modelsim_ase/linuxaloem/../altera/vhdl/src/altera_mf/altera_mf.vhd#  ** Fatal: (vsim-3363) /home/work/Desktop/Quartus_projects/workswell/LVDS_DESER/db/ip/temp_table/submodules/temp_table_onchip_memory2_0.v(85): The array length (1) of VHDL port 'data_a' does not match the width (32) of its Verilog connection (9th connection).#     Time: 0 ps  Iteration: 0  Instance: /tau2_temp_calculate_tb/tau2_temp_calculate_inst/temp_table_inst/onchip_memory2_0/the_altsyncram File: /home/work/intelFPGA_lite/16.1/modelsim_ase/linuxaloem/../altera/vhdl/src/altera_mf/altera_mf.vhd Line: 39911

altera_forum · Answer

The error messages indicate "missing Verilog connection for formal VHDL port."  Are you missing some connections?  What does the code to instantiate this look like?

altera_forum · Answer

Hello,

Thank you for your reply, you can find the code to instantiate the component below. I do not think I left anything unconnected, as you can see on the picture attached(I unchecked the reset request option on generation).

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY tau2_temp_calculate IS

PORT( onchip_memory2_0_clk1_clk : IN STD_LOGIC;

onchip_memory2_0_s1_address : IN STD_LOGIC_VECTOR(13 DOWNTO 0);

onchip_memory2_0_s1_readdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

onchip_memory2_0_clk2_clk : in std_logic;

onchip_memory2_0_reset2_reset : in std_logic; -- onchip_memory2_0_reset2.reset

onchip_memory2_0_s2_address : in std_logic_vector(13 downto 0); -- onchip_memory2_0_s2.address

onchip_memory2_0_s2_chipselect : in std_logic; -- .chipselect

onchip_memory2_0_s2_clken : in std_logic; -- .clken

onchip_memory2_0_s2_write : in std_logic; -- .write

onchip_memory2_0_s2_readdata : out std_logic_vector(31 downto 0); -- .readdata

onchip_memory2_0_s2_writedata : in std_logic_vector(31 downto 0); -- .writedata

onchip_memory2_0_s2_byteenable : in std_logic_vector(3 downto 0);

onchip_memory2_0_reset1_reset : in std_logic;

onchip_memory2_0_s1_clken : in std_logic;

onchip_memory2_0_s1_chipselect : in std_logic;

onchip_memory2_0_s1_write : in std_logic;

onchip_memory2_0_s1_writedata : in std_logic_vector(31 downto 0);

onchip_memory2_0_s1_byteenable : in std_logic_vector(3 downto 0)

);

END tau2_temp_calculate;

ARCHITECTURE bdf_type OF tau2_temp_calculate IS

COMPONENT temp_table

port (

onchip_memory2_0_clk1_clk : in std_logic;

onchip_memory2_0_clk2_clk : in std_logic;

onchip_memory2_0_reset1_reset : in std_logic;

onchip_memory2_0_reset2_reset : in std_logic;

onchip_memory2_0_s1_address : in std_logic_vector(13 downto 0);

onchip_memory2_0_s1_clken : in std_logic;

onchip_memory2_0_s1_chipselect : in std_logic;

onchip_memory2_0_s1_write : in std_logic;

onchip_memory2_0_s1_readdata : out std_logic_vector(31 downto 0);

onchip_memory2_0_s1_writedata : in std_logic_vector(31 downto 0);

onchip_memory2_0_s1_byteenable : in std_logic_vector(3 downto 0);

onchip_memory2_0_s2_address : in std_logic_vector(13 downto 0);

onchip_memory2_0_s2_chipselect : in std_logic;

onchip_memory2_0_s2_clken : in std_logic;

onchip_memory2_0_s2_write : in std_logic;

onchip_memory2_0_s2_readdata : out std_logic_vector(31 downto 0);

onchip_memory2_0_s2_writedata : in std_logic_vector(31 downto 0);

onchip_memory2_0_s2_byteenable : in std_logic_vector(3 downto 0)

);

END COMPONENT;

begin

temp_table_inst: temp_table

PORT MAP(

onchip_memory2_0_s1_readdata=> onchip_memory2_0_s1_readdata,

onchip_memory2_0_s1_address => onchip_memory2_0_s1_address,

onchip_memory2_0_clk1_clk=>onchip_memory2_0_clk1_clk,

onchip_memory2_0_reset1_reset=>onchip_memory2_0_reset1_reset,

onchip_memory2_0_s1_clken => onchip_memory2_0_s1_clken,

onchip_memory2_0_s1_chipselect=> onchip_memory2_0_s1_chipselect,

onchip_memory2_0_s1_write => onchip_memory2_0_s1_write,

onchip_memory2_0_s1_writedata=> onchip_memory2_0_s1_writedata,

onchip_memory2_0_s1_byteenable=> onchip_memory2_0_s1_byteenable,

onchip_memory2_0_clk2_clk =>onchip_memory2_0_clk2_clk,

onchip_memory2_0_reset2_reset => onchip_memory2_0_reset2_reset,

onchip_memory2_0_s2_address => onchip_memory2_0_s2_address,

onchip_memory2_0_s2_chipselect => onchip_memory2_0_s2_chipselect,

onchip_memory2_0_s2_clken => onchip_memory2_0_s2_clken,

onchip_memory2_0_s2_write => onchip_memory2_0_s2_write,

onchip_memory2_0_s2_readdata =>onchip_memory2_0_s2_readdata,

onchip_memory2_0_s2_writedata => onchip_memory2_0_s2_writedata,

onchip_memory2_0_s2_byteenable => onchip_memory2_0_s2_byteenable

);

END bdf_type;

altera_forum · Answer

The code for my testbench is:

LIBRARY altera_mf ;

LIBRARY ieee ;

LIBRARY std ;

USE altera_mf.all ;

USE ieee.std_logic_1164.all ;

USE ieee.std_logic_textio.all ;

USE ieee.std_logic_unsigned.all ;

use ieee.numeric_std.all;

USE std.textio.all ;

ENTITY tau2_temp_calculate_tb IS

END ;

ARCHITECTURE tau2_temp_calculate_tb_arch OF tau2_temp_calculate_tb IS

SIGNAL onchip_memory2_0_clk1_clk : STD_LOGIC;

SIGNAL onchip_memory2_0_s1_address : STD_LOGIC_VECTOR(13 DOWNTO 0);

SIGNAL onchip_memory2_0_s1_readdata : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL onchip_memory2_0_clk2_clk : std_logic;

SIGNAL onchip_memory2_0_reset2_reset : std_logic;

SIGNAL onchip_memory2_0_s2_address : std_logic_vector(13 downto 0);

SIGNAL onchip_memory2_0_s2_chipselect : std_logic;

SIGNAL onchip_memory2_0_s2_clken : std_logic;

SIGNAL onchip_memory2_0_s2_write : std_logic;

SIGNAL onchip_memory2_0_s2_readdata : std_logic_vector(31 downto 0);

SIGNAL onchip_memory2_0_s2_writedata : std_logic_vector(31 downto 0);

SIGNAL onchip_memory2_0_s2_byteenable : std_logic_vector(3 downto 0);

SIGNAL onchip_memory2_0_reset1_reset : std_logic;

SIGNAL onchip_memory2_0_s1_clken : std_logic;

SIGNAL onchip_memory2_0_s1_chipselect : std_logic;

SIGNAL onchip_memory2_0_s1_write : std_logic;

SIGNAL onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0);

SIGNAL onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0);

COMPONENT tau2_temp_calculate

PORT(

onchip_memory2_0_clk1_clk : IN STD_LOGIC;

onchip_memory2_0_s1_address : IN STD_LOGIC_VECTOR(13 DOWNTO 0);

onchip_memory2_0_s1_readdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

onchip_memory2_0_clk2_clk : in std_logic;

onchip_memory2_0_reset2_reset : in std_logic; -- onchip_memory2_0_reset2.reset

onchip_memory2_0_s2_address : in std_logic_vector(13 downto 0); -- onchip_memory2_0_s2.address

onchip_memory2_0_s2_chipselect : in std_logic; -- .chipselect

onchip_memory2_0_s2_clken : in std_logic; -- .clken

onchip_memory2_0_s2_write : in std_logic; -- .write

onchip_memory2_0_s2_readdata : out std_logic_vector(31 downto 0); -- .readdata

onchip_memory2_0_s2_writedata : in std_logic_vector(31 downto 0); -- .writedata

onchip_memory2_0_s2_byteenable : in std_logic_vector(3 downto 0);

onchip_memory2_0_reset1_reset : in std_logic;

onchip_memory2_0_s1_clken : in std_logic;

onchip_memory2_0_s1_chipselect : in std_logic;

onchip_memory2_0_s1_write : in std_logic;

onchip_memory2_0_s1_writedata : in std_logic_vector(31 downto 0);

onchip_memory2_0_s1_byteenable : in std_logic_vector(3 downto 0)

);

END COMPONENT;

BEGIN

tau2_temp_calculate_inst: tau2_temp_calculate

PORT MAP(

onchip_memory2_0_clk1_clk =>onchip_memory2_0_clk1_clk,

onchip_memory2_0_s1_address =>onchip_memory2_0_s1_address,

onchip_memory2_0_clk2_clk =>'0',

onchip_memory2_0_reset2_reset=>'0',

onchip_memory2_0_s2_address=>(others => '0'),

onchip_memory2_0_s2_chipselect=>'0',

onchip_memory2_0_s2_clken=>'0',

onchip_memory2_0_s2_write=>'0',

onchip_memory2_0_s2_readdata=>onchip_memory2_0_s2_readdata,

onchip_memory2_0_s2_writedata=>(others => '0'),

onchip_memory2_0_s2_byteenable=>(others => '0'),

onchip_memory2_0_reset1_reset=>'0',

onchip_memory2_0_s1_clken => '1',

onchip_memory2_0_s1_chipselect=> '1',

onchip_memory2_0_s1_write => '0',

onchip_memory2_0_s1_writedata => "00000000000000000000000000000000",

onchip_memory2_0_s1_byteenable=> (others => '1')

);

Process

variable DataIN : unsigned(13 downto 0);

Begin

DataIN:=to_unsigned(0,DataIN'length);

for Z in 1 to 16383

loop

onchip_memory2_0_s1_address <= std_logic_vector(DataIN) ;

wait for 47532 ps;

DataIN:=DataIN+to_unsigned(1,DataIN'length);

end loop;

wait;

End Process;

Process

Begin

for Z in 1 to 16383

loop

onchip_memory2_0_clk1_clk <= '1' ;

wait for 23766 ps ; --"1" period:1/2*(10^12/147.27*10^6)

onchip_memory2_0_clk1_clk <= '0' ;

wait for 23766 ps ; --"0" period:1/2*(10^12/147.27*10^6)

end loop;

wait;

End Process;

END;

altera_forum · Answer

I think I found a possible cause for the problem. I am using Modelsim Starter Edition, my surrounding code is in VHDL, while the code generated by Qsys is in verilog. The Starter Edition for what I´ve seen does not support mixed-language simulation, so this may well be at the root of the problem. Does anyone know whether it is possible to generate the tempcalc_onchip_memory2.0.v and the functions used in it in VDHL instead of verilog? Choosing to create HDL design files for synthesis does not change this generated file.

UPDATE:

I have recreated my surrounding modules in verilog(there are some decent VHDL->verilog converters online, I chose vhd2vl), and run the simulation with those, generating the whole qsys module in verilog too. The simulation works without a problem now.

altera_forum · Answer

--- Quote Start ---

I think I found a possible cause for the problem. I am using Modelsim Starter Edition, my surrounding code is in VHDL, while the code generated by Qsys is in verilog. The Starter Edition for what I´ve seen does not support mixed-language simulation, so this may well be at the root of the problem. Does anyone know whether it is possible to generate the tempcalc_onchip_memory2.0.v and the functions used in it in VDHL instead of verilog? Choosing to create HDL design files for synthesis does not change this generated file.

UPDATE:

I have recreated my surrounding modules in verilog(there are some decent VHDL->verilog converters online, I chose vhd2vl), and run the simulation with those, generating the whole qsys module in verilog too. The simulation works without a problem now.

--- Quote End ---

To fix this issue the "altera_mf_ver" library must be called before the "altera_mf" library.

For example

vsim -t ps -novopt -L altera_mf_ver -L altera_mf

Forum Discussion

Dual-port access avalon memory simulation problem

5 Replies

Recent Discussions

Quartus Prime Pro 25.1 fatal error during fitter: Windows "Efficiency mode" required

Step Load conditions

R-Tile Avalon Streaming PIPE Direct x16: Locks COM(K28.5) Symbols correctly but some lanes do not.

MAX10 Dual Configuration

Agilex 5: Cascading DSPs in tensor-mode doesn't work